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[ET-VK][runtime] Make output staging visible to the host before readback - #24910

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Nov 11, 2026
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SS-JIA merged 1 commit into
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gh/SS-JIA/712/orig

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This PR was created by the merge bot to help merge the original PR into the main branch.
ghstack PR number: #24865 by @SS-JIA
^ Please use this as the source of truth for the PR details, comments, and reviews
ghstack PR base: https://github.com/pytorch/executorch/tree/gh/SS-JIA/712/base
ghstack PR head: https://github.com/pytorch/executorch/tree/gh/SS-JIA/712/head
Merge bot PR base: https://github.com/pytorch/executorch/tree/gh/SS-JIA/711/orig
Merge bot PR head: https://github.com/pytorch/executorch/tree/gh/SS-JIA/712/orig
Differential Revision: D130959944
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Pull Request resolved: #24865

## Ulterior Motive

Found while preparing zero-copy graph I/O through app-provided GPU resources, added in the next commit. That commit also needs global memory barriers for memory the graph does not track, so this one adds them first.

## Rationale

**What**: End each recorded graph execution with a global memory barrier from all GPU writes to host reads. To record it, `vkapi::PipelineBarrier` gains `global_access` masks, recorded as a `VkMemoryBarrier`.

**Why**: The host reads output staging buffers once `execute()` returns, after a fence wait. A fence wait alone does not make the GPU's writes visible to the host. The Vulkan spec's note under `vkWaitForFences`:

> Signaling a fence and waiting on the host does not guarantee that the results of memory accesses will be visible to the host, as the access scope of a memory dependency defined by a fence only includes device access. A memory barrier or other memory dependency must be used to guarantee this.

`StagingBuffer` already calls `vmaInvalidateAllocation` before reading. That covers only device writes already made available to the host memory domain through `VK_ACCESS_HOST_READ_BIT`, which takes the barrier added here. Output staging prefers `HOST_CACHED` memory, which is often non-coherent.

## Details

- Graph execution
  - **Before**: the last command buffer ended with the last node's commands.
  - **After**: it ends with an `ALL_COMMANDS`/`MEMORY_WRITE` → `HOST`/`HOST_READ` barrier. The barrier is recorded once with the command buffers and replayed on every `execute()`. Its source scope covers the command buffers that large graphs submit earlier without a fence.
- `PipelineBarrier`
  - **Before**: buffer and image barriers only.
  - **After**: optional `global_access` masks. `CommandBuffer::record_barrier()` records a `VkMemoryBarrier` when either mask is set; existing barriers leave both zero and record as before.

No failure was observed without the barrier: in practice, drivers flush GPU caches when a submission completes. The spec does not guarantee it.

Inputs need no change: queue submission makes earlier host writes visible to the device, and `StagingBuffer` flushes non-coherent memory after writing.

Test utilities that submit work and read staging without `ComputeGraph::execute()` keep the gap.

This diff was authored with Claude Code.
ghstack-source-id: 470836157
@exported-using-ghexport

Differential Revision: [D130959944](https://our.internmc.facebook.com/intern/diff/D130959944/)

**NOTE FOR REVIEWERS**: This PR has internal Meta-specific changes or comments, please review them on [Phabricator](https://our.internmc.facebook.com/intern/diff/D130959944/)!
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pytorchbot requested a review from SS-JIA as a code owner November 11, 2026 20:14
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🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/24910

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@meta-cla meta-cla Bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Nov 11, 2026
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SS-JIA added this pull request to stack #24913 November 11, 2026 20:29
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SS-JIA merged commit abc61a0 into main Nov 11, 2026
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SS-JIA deleted the gh/SS-JIA/712/orig branch November 11, 2026 21:10

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